The present invention relates to a multilayer wiring board for mounting a semiconductor chip thereon and, in particular, to a flexible multilayer wiring board with high density wiring (buildup flexible multilayer wiring board), and further relates to a manufacture method for easily manufacturing such a board.
In recent years, higher integration and higher performance have been increasingly required for semiconductor devices, and the increase in numbers of terminals thereof has also been remarkable. For example, in case of surface mount packages such as a QFP (Quad Flat Package), the increased numbers of terminals have been achieved by narrowing the pitches of external terminals without enlarging the package sizes. However, following the narrowing of the external terminal pitches, the width of each external terminal itself is reduced to lower a strength thereof. As a result, it becomes difficult to cope with the skew of the external terminals and maintain the flatness thereof in a later process such as forming. Thus, there has been a problem of difficulty in ensuring the mounting accuracy of semiconductor packages.
For coping therewith, those packages represented by a BGA (Ball Grid Array) have been developed, wherein a multilayer wiring board is used as an interposer. The BGA is normally mounted with a semiconductor chip on one side of the board and provided with spherical solder balls on the other side thereof as external connection terminals, thereby to ensure electrical connection between terminals of the semiconductor chip and the external connection terminals (solder balls), and thus is a package that aims improvement in mountability.
On the other hand, the bare chip mounting method has been recently proposed wherein a chip not packaged (bare chip) is directly mounted onto a multilayer wiring board. In the bare chip mounting method, a semiconductor device chip is mounted onto a connection pad portion of wiring formed on a multilayer wiring board in advance. Inasmuch as the chip is not sealed in a package as noted above, conducting paths between the wiring of the multilayer wiring board and the chip can be simplified and shortened. Further, since the mounting density is improved, distances to other chips can also be shortened. Therefore, not only reduction in size and weight, but also high-speed signal processing can be expected.
In general, multilayer wiring boards used in such a bare chip mounting method are manufactured by using, as a core board, a double-sided board having low density wiring formed by the subtractive method or the like, and forming high density wiring on each side of the core board by the buildup method.
However, the formation of the high density wiring using the buildup method requires complicated processes, and it has been difficult to produce the high density wiring with a line/space width being 25 μm/25 μm or less. Specifically, the conventional buildup method requires complicated processes, such as a process of forming a power feeding layer on the roughened surface of a resin layer by electroless plating, a process of forming a wiring pattern by providing a plating resist on the power feeding layer and performing electrolytic plating, and a process of flash etching (electroless plating layer removing process) that is carried out thereafter. Further, in the formation of the fine wiring with a line/space width being 25 μm/25 μm or less, there has been a problem that a short circuit is liable to occur due to the residue of the electroless plating layer caused upon removal thereof by the flash etching, leading to difficulty in ensuring reliability.
There has been disclosed a manufacture method, wherein circuit wiring is formed on a copper substrate by electrolytic plating, an insulating layer is formed so as to cover the circuit wiring, hole portions for formation of external terminals are provided in the insulating layer, then, after forming the terminals in the hole portions by electrolytic plating using the copper substrate as a power feeding layer, the copper substrate is selectively etched thereby to provide a lead frame (JP-A-H9-246445). According to this manufacture method, as opposed to the foregoing buildup method, inasmuch as the electroless plating process and the electroless plating layer removing process using the flash etching are unnecessary, the high density wiring with a line/space width being 25 μm/25 μm or less is made possible. However, since the lead frame obtained by this manufacture method has a single-layer structure, an obtained multi-pin LSI requires a large package size and thus it has been difficult to use it in an electronic device that highly requires reduction in size and weight. Further, it is impossible to manufacture a multilayer wiring board according to the foregoing manufacture method (JP-A-H9-246445).
On the other hand, the foregoing conventional multilayer wiring board has a limit in reducing the size and weight because of use of the core board. For example, there has been a problem of being unable to satisfy the demand for reduction in size and weight in small communication devices and so forth. In view of this, a flexible multilayer wiring board is considered wherein circuit wirings are formed in multilayers via insulating layers made of polyimide or the like without using the core board. However, in stacking the circuit wirings using the conventional buildup method, there has been a problem, in addition to the foregoing problem relating to the electroless plating process and the flash etching process, that a power feeding layer having an excellent adhesion relative to polyimide can not be formed by electroless plating. As described above, such a flexible multilayer wiring board that can be used practically, particularly such a flexible multilayer wiring board that is provided with high density wiring, has not yet been achieved, and thus the flexible multilayer wiring board that can be put to practical use has been desired for the purpose of realizing further reduction in size and weight in the small communication devices and so forth.